Balanced optically settable memory cell

ABSTRACT

An optically settable memory cell includes two MOS transistors each having a gate cross-coupled to the drain of the other transistor to provide a bistable circuit. Each transistor has a drain extending over an area of the substrate to form a photodiode. Bias potential is applied to the sources as well as the drains of the two transistors to render them nonconductive and to charge both photodiodes to the same reverse bias potential. The application of potential to the drains is interrupted while a differential input light signal is applied to the photodiodes to cause an unequal discharging of the photodiodes. Potential is then removed from the sources and restored to the drains, whereby the transistor having its gate connected to the photodiode having the greater charge is rendered conductive, and the transistors then store an optically determined information bit.

United States Patent [72] Inventor Walter Frank Kosonocky Skillman, NJ. [21] Appl. No. 81,966

[ 22] Filed [45] Patented [73] Assignee Oct. 19, 1970 Nov. 30, 1971 RCA Corporation [54] BALANCED OPTICALLY SETTABLE MEMORY [56] References Cited UNITED STATES PATENTS 3,165,633 1/1965 Wunderman et al. 307/311 X 3,348,064 10/1967 Powlus 307/205 Primary Examiner-John S. Heyman Attorney-H. Christofiersen ABSTRACT: An optically settable memory cell includes two MOS transistors each having a gate cross-coupled to the drain of the other transistor to provide a bistable circuit. Each transistor has a drain extending over an area of the substrate to form a photodiode. Bias potential is applied to the sources as well as the drains of the two transistors to render them nonconductive and to charge both photodiodes to the same reverse bias potential. The application of potential to the drains is interrupted while a differential input light signal is applied to the photodiodes to cause an unequal discharging of the photodiodes. Potential is then removed from the sources and restored to the drains, whereby the transistor having its gate connected to the photodiode having the greater charge is rendered conductive, and the transistors then store an optically determined information bit.

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SHEEI 2 0F 4 Him 6 7 I. F16. Whiter E Ko gify BY ATTORNEY BALANCED OPTICALLY SETTABLE MEMORY CELL The invention herein described was made in the course of, or under a contract or subcontract thereunder, with the Department of the Air Force.

BACKGROUND OF THE INVENTION In the field of data processing and information systems, bistable semiconductor circuits or flip-flops are often used in registers and in memory arrays to store a corresponding number of binary information bits. Such registers and memory arrays are electrically accessible for the writing of binary information thereinto, and for the reading out of binary information therefrom. There is an increasing interest in computer systems including components in which binary infonnation is also represented by optical or light signals, rather than electrical signals. It is then desirable to provide means for using a light s gnal to set a flip-flop. Such an Optically Settable Flip- Flop" is described in US. Pat. application Ser. No. 866,565 filed on Oct. 15, 1969 by the same inventor and assigned to the same assignee as the present case.

SUMMARY OF THE INVENTION An improved semiconductor bistable circuit is provided which is electrically accessible in the usual way, and which is also capable of being set to one or the other of its two stable states in response to input light signals. The preferred embodiment of the circuit includes two cross coupled insulated gate field effect transistors, and two photodiodes connected in a balanced fashion to control the states of the transistors in response to the difierential effect of two input light signals. The balanced circuit is an order of magnitude more sensitive than known prior arrangements operating on the presence or absence of a single input light signal.

BRIEF DESCRIPTION OF THE DRAWING FIG. I is a circuit diagram of an electrically and optically settable flip-flop constructed according to the teachings of the invention;

FIG. 2 is a chart of voltage waveforms which will be referred to in describing the operation of the circuit of FIG. 1;

FIG. 3 is a plan view of an integrated circuit embodiment of the circuit of FIG. 1;

FIG. 4 is a sectional view taken on the line 4-4 in FIG. 3;

FIG. 5 is a circuit diagram of an electrically and optically settable flip-flop of the type requiring only intermittent application of bias potential;

FIG. 6 is a chart of voltage waveforms which will be referred to in describing the operation ofthe circuit of FIG. 5; and

FIG. 7 is a plan view of an integrated circuit embodiment of the circuit of FIG. 5.

DESCRIPTION OF FIGS. 1, 3 and 4 Referring now in greater detail to FIG. I, there is shown an electrically and optically settable bistable circuit or flip-flop. The flip-flop portion of the circuit includes cross-coupled transistors T, and t and load impedance transistors t and t, for the transistors T, and T respectively The load impedance transistors T, and t are connected to a switchable source V,, of bias potential capable of supplying either a V bias potential or a reference or ground potential. The transistors T,, T T and T are illustrated as P-type MOS (metal oxide semiconductor) insulated gate field effect transistors (IGFETS). Each transistor includes, as shown in relation to transistor T,., a source 7, a drain 8, and a gate electrode 9. The described circuit including transistors T,, T T and T constitutes a known bistable circuit or flip-flop.

The flip-flop is shown connected as one memory cell in an array of memory cells which includes means for electrically writing an information bit into the memory cell and reading out an information bit from the memory cell. The accessing means includes a digit drive and sense circuit DS connected to a digit column line d and a digit driver and sense circuit DS, connected to a digit column line (1,. The accessing means also includes a word driver w connected to a word row line W and a word driver W, connected to a word row line w,. Separate word lines w and w, are shown in FIG. I because they may be needed to insure geometrical symmetry in the actual circuit layout, such as the layout shown in FIG. 3. Otherwise, a single word driver and a single word line may replace drivers W and W, and word lines W and w,.

The digit line d is coupled through a gate transistor T, to the drain 22 or output A of transistor T,, and to the gate electrode 9 of transistor T,. The gate transistor T is enabled by a signal applied to the gate electrode thereof from the word line w The digit line d, is coupled through a gate transistor T. to the drain 8 or output B of transistor T, and to the gate electrode ll of transistor T,. Gate transistor T is enabled by a signal from the word line w,.

The circuit of FIG. 1 also includes a PN photodiode D having one side, an anode 13, connected to the drain 22 or output A of transistor T,, and to the gate 9 of transistor T The diode D, has another side or cathode 14 connected to a point of reference potential which is the bulk silicon substrate of transistor T,. When circuit is built in integrated form, the built silicon substrate is common also to transistors T through T,,. A second photodiode D, has an anode connected to the drain 8 of transistor T and to the gate electrode of transistor T,.

FIGS. 3 and 4 show a physical construction of the electrically and optically settable memory element shown in circuit diagram form in FIG. 1. The circuit is constructed on an N- type silicon substrate 20 in which regions of P+ silicon are formed to serve as source and drain elements of the transistors. The P+ regions and the regions therebetween are covered with a layer of silicon dioxide, $0,, to provide electrical insulation. Conductive gate electrodes are formed over the insulated regions between respective sources and drains. Electrical conductors, formed on the silicon dioxide layer, include contact regions, such as 24, extending through openings in the silicon dioxide layer to the P+ regions below.

The transistors T, through T shown in FIG. I are indicated in FIG. 3 by the same respective designations T, through T The transistor T, is seen from FIGS. 3 and 4 to include a P+ type source 21 separated from a P+ type drain 22. A thin silicon dioxide layer overlying the area between the source 21 and the drain 22 forms an insulating region over which is positioned a conductive gate electrode 11. The digit conductor lines d and d, are shown on top of the silicon dioxide layer. A ground line g is shown on the silicon dioxide layer with a contact region 24 extending through the silicon dioxide layer to make electrical contact with the P+ material forming the source 21 of transistor T,. The construction of gate transistors T, and T and load impedance transistors T and T are also shown in FIG 3.

Transistors T and T are made large and of low-impedance relative to gate transistors T and T which, in turn, are large and of low impedance relative to load impedance transistors T and T The size of an MOS transistor is determined by the ratio of the width of the channel to the length of the channel. In accordance with these design considerations, the transistors T, and T in FIG. 3 are seen to have channels which are relatively wide and short in length. Transistors T and T on the other hand, have channels that are relatively narrow and long.

The drain 22 of transistor T, is shown in FIGS. 3 and 4 to be a H material which is extended along the N-type substrate 20 to a relatively large rectangular area to form the photodiode D The H material in this area forms the anode 13 of the photodiode D and the N-type substrate material 20 forms the cathode 14 of the photodiode D. The large surface of the P-lmaterial forming the photodiode D is covered with a thin layer of silicon dioxide having a thickness equal to about onefourth the wavelength of the light signal L so that reflections of the light signal at the surface of the silicon are minimized. The photodiode D, is similarly constructed in relation to transistor T to be symmetrical with photodiode D and transistor T,.

To complete the structural description, the bottom surface of the N-type silicon 20 may be provided with a thin N+ layer 26 on which is formed a metal ground layer 28. The metal ground layer 28 is externally connected to the ground conductor g on the top surface of the integrated circuit. Since the construction of MOS integrated circuits is generally known, it is not necessary to describe the construction shown in FIGS. 3 and 4 in greater detail.

OPERATION OF FIG. I

The operation of the circuit of FIG. I will now be described with references to the waveforms of FIG. 2. The flipflop is assumed at time to be in its 37 set" condition with transistor T, conducting and transistor T, cut off. The set condition of the flip-flop may have been electrically caused by applying a negative pulse to the digit line d, concurrently with the application of a negative pulse through the word line w, to the gate of transistor T,. The negative pulse passed by the gate transistor T is applied to the gate electrode of transistor T,. This makes transistor T, conductive, and, through regenerative action of the cross coupled transistors, makes transistor T nonconductive.

In order to make the circuit responsive to light, it is necessary to first charge both photodiodes D, and D to the same value of a reverse bias potential V. At time 1,, the potential on the sources of transistors T, and T is changed from ground or reference potential to a potential equal to or somewhat more negative than V, as shown in waveform V, in FIG. 2. Simultaneously, transistors T, and T, are enabled from word drivers W and W, to couple V potentials from digit drivers D8,, and DS, to the anodes of photodiodes D, and D Therefore, at the end of the interval between I, and t transistors T, and T are rendered nonconducting because the potential supplied to their sources from V, is equal to or more negative than the potential supplied to their drains from D5,, and D8,. The photodiodes D and D, are then charged equally to the potential V present at points A and B.

To make the photodiodes responsive solely to input light signals during the interval between I, and it is necessary to electrically isolate the anodes of diodes D, and D to prevent their being maintained in a charged state by current from any electrical source. After time 1 potential is no longer supplied from bias source V through load transistors T and T,,, as shown by waveform V,, in FIG. 2. Transistors T and T, are cut ofi by signals from word drivers W and W, as shown in waveforms labeled W and W, in FIG. 2. The photodiodes are then, at time 1 charged to V volts as shown by waveforms V, and V in FIG. 2, and are electrically isolated from all sources of potential. The circuit is then ready to receive an input light signal which will result in the storage of a l or a 0" information bit in the bistable circuit after bias potential is reapplied.

The input light signal consists of light L, and directed to photodiode D,, or light I.. directed to photodiode D. Light falling on a photodiode causes a proportionate discharging of the photodiode in the interval between and i If the input light signal consists solely of light L directed to photodiode D,,, the charge on the anode 13 decreases toward zero as shown at 16 in waveform V, of FIG. 2, and the charge on diode D, decreases toward zero at a much slower rate as shown at 17 in waveform V,, of FIG. 2. The decrease in charge in photodiode D, may be due entirely to leakage in the semiconductor material, or may be partially due to ambient or stray light impinging on photodiode D,. The light sources supplying light L, and L, may be imperfect in that they cannot be switched between conditions of no light output and full light output. Then the unequal input light may be considered to be a differential light signal. In any case, there is an unequal or differential discharging of the photodiodes D, and D The input light signal cannot cause the potential on one photodiode to differ from the potential on the other photodiode by more than the threshold voltage of the transistors T, and T,. If the difference in potential exceeds the threshold value, one of the transistors wili be rendered conductive enough in the reverse direction (from drain to source) to limit the potential difference to the threshold value. This is because the potential difierence is coupled from the diodes to across the gate and drain electrodes of the transistors.

At time 1 the sources of transistors T, and T, are returned to ground potential by the operation of driver V,,, and the drains of transistors T, and T are supplied with bias potential by operation of bias source V,,, as shown in waveforms V, and V, of FIG. 2. Then the transistors T, and T, start conducting at rates determined by the amounts of the charges coupled to the gates thereof from the anodes of the photodiodes D, and D Since it has been assumed that light L, was greater than light L,, diode D, has retained a greater negative charge than diode D and therefore transistor T, initially conducts more than transistor T The greater conduction in transistor T,, because of the crosscoupling between the transistors, causes transistor T to conduce less. The changes continue in a rapid regenerative manner until transistor T, conducts fully and transistor T is cut off. The bistable circuit then stores the optically-supplied l" information signal. If the input light signal L, had been greater than L the result would have been the rendering of transistor T conductive and the storage of a 0" information signal in the bistable circuit.

DESCRIPTION of FIGS. 5 AND 7 Reference is now made to FIG. 5 for a description of an electrically and optically settable bistable circuit which is the same as the circuit of FIG. I except that the bias source V, is omitted, and the load impedance transistors T and T are omitted. The elements in FIG. 5 are given the same numerals and designations as corresponding elements in FIG. I.

The bistable circuit of FIG. 5 is electrically set to one or the other of its two information states by electrical signals applied from digit drivers D8,, and DS, through gate transistors T and T when enabled by signals from word drivers W and W The transistors T and T, act as also load impedance transistors and the electrical signals cause one of transistors T, and T to be conducting and the other to be nonconducting. In this condition, the drain of the nonconducting one of transistors T, and T, has an electrical charge relative to the semiconductor substrate. This charge gradually leaks away when the digit drive voltages are removed. However, potentials from the digit drivers may be periodically reapplied to utilize the remaining charge to reestablish or refresh the stored information state of the bistable circuit. This refreshment may be accomplished at intervals of milliseconds or even seconds, depending on the rate of charge leakage in the substrate.

FIG. 7 shows the layout of the elements of the circuit of FIG. 5 on a semiconductor substrate. The layout of elements in FIG. 7 is such that there is complete symmetry between the two sides of the bistable circuit. A symmetrical layout is desirable in order to insure that the charges on the two photodiodes D, and D, are initially established at the same potential, are not unequally affected by applied potentials, and the photodiodes are discharged solely in proportion to the amounts of input signal light impinging thereon.

OPERATION OF FIG. 5

The operation of the bistable circuit of FIG. 5 is similar to the operation of the circuit of FIG. 1, except that solely gate transistors T and T, are available for applying potentials through points A and B to the drains and gates of transistors T, and T,.

It is assumed that, at time 1,, in FIG. 6, the bistable circuit is in the state in which transistor T, is fully conducting by reason of the prior application of a V potential through gate transistor T, to the gate electrode 11 of transistor T,. Transistor T is nonconducting because of the cross connection from the drain 22 of transistor T, to the gate 9 of transistor T,.

5 At time 1,, a V bias potential is coupled from digit drivers D8,, and DS, through gate transistors T and T,, which are enabled by signals from word drivers W and W,, to the drains of transistors T, and T The corresponding waveforms are labeled D5,, DS W, and W,, in FIG. 6. At the same time t a substantially equal or greater negative potential is applied from potential source V, over ground line 3 to the sources of transistors T, and T Under these conditions, the sources of potential tend to establish a zero or reverse potential difference across the source and drain electrodes of transistors T, and T and the previously conducting transistor T, is thus also rendered nonconducting at time In this interval between time t, and t the negative potentials applied to points A and B cause a charging of the photodiodes D, and D until both photodiodes are equally charged to the potential V, as shown by waveforms V and V At time 1 the application of potential to the drains of transistors T, and T is interrupted by an interruption of the enabling potentials to the gates of transistors T and T, from the word drivers W and W,. Then, in the interval between 2 and a difierential input light signal is applied to the photodiodes D, and D to cause an unequal discharging of the photodiodes. It is assumed that light signal L, is greater than light signal L, so that photodiode D is discharged at a greater rate than photodiode D,. The relatively greater discharging of the charge on photodiode D is represented at 16 in waveform V in FIG. 6, relative to the discharging of the photodiode D, as represented at 17 in waveform V of FIG. 6. During this discharging of the photodiodes as a result of impinging light signals, the photodiodes are electrically isolated from sources of potential that might otherwise affect the charges thereon.

At time the negative potential previously applied over line g to the sources of transistors T, and T is discontinued, and bias potential is restored through points A and B to the drains of transistors T, and T When this occurs, the photodiode still having the greater negative charge tends to render the associated transistor conducting. In the present example, photodiode D, retains the greater negative charge, which is applied to the gate electrode 11 of transistor T, and tends to make the transistor conductive With every increment of conduction in transistor T,, there is a regenerative feedback from the drain 22 of the transistor T, through point A to the gate electrode of transistor T; which tends to reduce conduction in transistor T The circuit thus quickly assumes a condition in which transistor T, is fully conductive and transistor T is nonconductive. The circuit then is in the condition of electrically storing the optically determined 1" information bit supplied by the differential input light signal L, and L Thereafter, the stored information may be read out electrically in the usual known manner, and the procedure for receiving the next subsequent input light signal may be repeated, Of course, if the potential L, of the input light signal had been greater than the potential of L the transistor T would have been rendered solely conductive, with transistor T, cut off, to store the other or 0" information bit in the circurt.

The sensitivity of the optically settable bistable circuits of FIGS. 1 and depends on the degree of symmetry and dimensional equivalence of the two sides of the circuits Sensitivity is also increased when the transistors T, and T are constructed to have the same threshold voltages.

While the invention has been described as being constructed using P-MOS field effect transistor technology, it will be understood that it can also be constructed by those skilled in the art using N-channel MOS, or complementary MOS technology. Further, the foregoing constructions can be of the bulk silicon type or the silicon-on-sapphire type.

What is claimed is:

1. An optically settable memory cell, comprising first and second lGF ET transistors having a substrate of one conductivity type, and each having a source and a drain of the opposite conductivity type, each transistor having a gate cross coupled to the drain of the other transistor, and

each transistor having a drain extending over an area of said substrate to form a photodiode,

means to couple a first potential to the drains of said first and second transistors,

means to apply a second potential of the same polarity to the sources of said transistors to render both transistors nonconductive and to charge both photodiodes to the same reverse bias potential,

means to interrupt the application of said first potential to said drains and to apply a differential input light signal to said photodiodes to cause an unequal discharging of said photodiodes, and

means to discontinue the application of said second potential to said sources and to restore said first potential to said drains, whereby the transistor having its gate connected to the photodiode having the greater charge is rendered conductive, and the transistors then store an optically determined information bit.

2. A memory cell as defined in claim 1 wherein said means to couple a first potential to the drains of the first and second transistors includes the source-drain paths of third and fourth transistors, respectively.

3. A memory cell as defined in claim 2, and in addition, digit lines connecting said first potential source through said third and fourth transistors to said first and second transistors, and word lines connected to the gates of said third and fourth transistors, whereby to render one or the other of said first and second transistors conductive for the storage of a l or 0 infon'nation bit.

4. A memory cell as defined in claim 1, and in addition, l and 0" digit lines connected through the source-drain paths of respective third and fourth transistors to the drains of said first and second transistors, and l and 0" word lines connected to gates of respective third and fourth transistors, whereby to render one or the other of said first and second transistors conductive for the storage of a l or 0" information bit.

5. A memory cell as defined in claim 4 wherein said means to couple a first potential to the drains of said first and second transistors includes fifth and sixth load impedance transistors, respectively.

6, A memory cell as defined in claim 1 wherein said means to couple a first potential to the drains of said first and second transistors includes two load impedance transistors.

7. An electrically and optically settable memory cell, comprising first and second MOS transistors having a substrate of one conductivity type, and each having a source and a drain of the opposite conductivity type, each transistors having a gate cross coupled to the drain of the other transistor to provide a bistable circuit, and each transistor having a drain extending over an area of said substrate to form a photodiode,

load impedance transistors coupling a first potential to the drains of said first and second transistors,

electrical signal input means including digit lines, word lines and third and fourth transistors to render one or the other of said first and second transistors conductive for the storage of an information bit,

means to apply a second potential of the same polarity to the sources of said first and second transistors to render both transistors nonconductive and to charge both photodiodes to the same reverse bias potential,

means to disconnect said first potential from said transistor impedance means and thereby interrupt the application of the first potential to the drains of said first and second transistors, and to apply a differential input light signal to said photodiodes to cause an unequal discharging of said photodiodes, and

means to discontinue the application of said second potential to the sources of said first and second transistors and to restore said first potential through the load impedance transistors to the drains of the first and second transistors,

whereby the transistor having its gate connected to the photodiode having the greater charge is rendered conductive, and the transistors then store an optically determined information bit.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,624,419 Dated November EL 1971 Walter Frank Knsnnocky It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Column 1, line 59, "t should read --T "12 should read ---T "t should read ---T line 60, after "respectively" insert line 61, "t should read ---T Column 2, line 2, "W should read -'-W line 23, after "when" insert -the-; line 23, "built" should read --bulk-; line 54, delete Column 3, line 14, delete "37"; line 14, before "set" insert line 515, delete "and"; line 56, "D" should read ---D Column 5, line 5, after "to" delete line 75, after "cross" insert Column 6, line 19, after "optically" insert line 52, after "cross" insert Column 7, line 3, after "optically" insert Signed and sealed this 1 8th day of July 1 972.

(SEAL) Attest:

EDWARD M.FLETCHER,JR. ROBERT GOTTSCHALK Attesting Officer Commissioner of Patents POWSO "$69) USCOMM-DC 60376-F'69 U75 GOVERNMENT PRINTING OFFICE III! O-SGG-Sl 

1. An optically settable memory cell, comprising first and second IGFET transistors having a substrate of one conductivity type, and each having a source and a drain of the opposite conductivity type, each transistor having a gate cross coupled to the drain of the other transistor, and each transistor having a drain extending over an area of said substrate to form a photodiode, means to couple a first potential to the drains of said first and second transistors, means to apply a second potential of the same polarity to the sources of said transistors to render both transistors nonconductive and to charge both photodiodes to the same reverse bias potential, means to interrupt the application of said first potential to said drains and to apply a differential input light signal to said photodiodes to cause an unequal discharging of said photodiodes, and means to discontinue the application of said second potential to said sources and to restore said first potential to said drains, whereby the transistor having its gate connected to the photodiode having the greater charge is rendered conductive, and the transistors then store an optically determined information bit.
 2. A memory cell as defined in claim 1 wherein said means to couple a first potential to the drains of the first and second transistors includes the source-drain paths of third and fourth transistors, respectively.
 3. A memory cell as defined in claim 2, and in addition, digit lines connecting said first potential source through said third and fourth transistors to said first and second transistors, and word lines connected to the gates of said third and fourth transistors, whereby to render one or the other of said first and second transistors conductive for the storage of a ''''1'''' or ''''0'''' information bit.
 4. A memory cell as defined in claim 1, and in addition, ''''1'''' and ''''0'''' digit lines connected through the source-drain paths of respective third and fourth transistors to the drains of said first and second transistors, and ''''1'''' and ''''0'''' word lines connected to gates of respective third and fourth transistors, whereby to render one or the other of said first and second transistors conductive for the storage of a ''''1'''' or ''''0'''' information bit.
 5. A memory cell as defined in claim 4 wherein said means to couple a first potential to the drains of said first and second transistors includes fifth and sixth load impedance transistors, respectively.
 6. A memory cell as defined in claim 1 wherein said means to couple a first potential to the drains of said first and second transistors includes two load impedance transistors.
 7. An electrically and optically settable memory cell, comprising first and second MOS transistors having a substrate of one conductivity type, and each having a source and a drain of the opposite conductivity type, each transistors having a gate cross coupled to the drain of the other transistor to provide a bistable circuit, and each transistor having a drain extending over an area of said substrate to form a photodiode, load impedance transistors coupling a first potential to the drains of said first aNd second transistors, electrical signal input means including digit lines, word lines and third and fourth transistors to render one or the other of said first and second transistors conductive for the storage of an information bit, means to apply a second potential of the same polarity to the sources of said first and second transistors to render both transistors nonconductive and to charge both photodiodes to the same reverse bias potential, means to disconnect said first potential from said transistor impedance means and thereby interrupt the application of the first potential to the drains of said first and second transistors, and to apply a differential input light signal to said photodiodes to cause an unequal discharging of said photodiodes, and means to discontinue the application of said second potential to the sources of said first and second transistors and to restore said first potential through the load impedance transistors to the drains of the first and second transistors, whereby the transistor having its gate connected to the photodiode having the greater charge is rendered conductive, and the transistors then store an optically determined information bit. 